A general logic circuit is configured using a special LSI (ASIC: Application Specific Integrated Circuit). However, a development cost for the ASIC is high, and its modification requires a lot of time and money. On the other hand, an FPGA (Field Programmable Gate Array) having simple logic configuration has been developed but is unsatisfactory in terms of power reduction and performance under present circumstances.
To that end, in general, the ASIC is designed with any extra logic circuit being previously incorporated thereinto to enable modification. This design can deal with a minor functional change flexibly to some extent.
A device disclosed in, for example, Patent Document 1 is well-known as a device to modify logic networks that undergoes a minor functional change. The device to modify logic networks discussed in Patent Document 1 is intended to modify an output value of a ROM storing a program to be executed with a CPU and is configured using the FPGA.
FIG. 20 show the configuration of a device to modify logic networks 103 described in Patent Document 1. A ROM 101 stores a program to be executed with a CPU 102. The CPU 102 sends an address to the ROM 101 through an address bus 104. The ROM 101 produces data to the address through a first data bus 106.
The device to modify logic networks 103 receives an address applied from the address bus 104 and receives corresponding data from the first data bus 106. A modification address storage unit 111 in the device to modify logic networks 103 registers an address of the ROM 101 where data to be modified is stored. A comparison circuit 113 determines whether the modification address storage unit 111 stores an address value that matches an address value applied from the address bus 104. If any address is matched, a match signal is produced; if no address is matched, a mismatch signal is produced. The match signal or mismatch signal is produced to a data selection circuit 114.
On the other hand, the modification data storage unit 112 registers data to be modified in association with each address value registered in the modification address storage unit 111. If a match signal is applied from the comparison circuit 113, the data selection circuit 114 produces data read from the modification data storage unit 112 to the second data bus 105. If a mismatch signal is applied, the data selection circuit 114 produces data applied from the first data bus 106 to the second data bus 105. The data produced to the second data bus 105 is applied to the CPU 102 as read data.
In this way, an address to be modified of the ROM 101 is registered in the modification address storage unit 111 and in addition, data to be modified is registered in the modification data storage unit 112 to thereby moderately change data in the ROM 101.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2002-297408    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2004-258799    Non-Patent Document 1: T. Sasao and M. Matsuura, “BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition”, Design Automation Conference, Anaheim, Calif., Jun. 13-17, 2005, pp. 373-378.